28 lines
491 B
Systemverilog
28 lines
491 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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module t;
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class B;
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function void B();
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endfunction
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endclass
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class A;
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B b = B::new();
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function void B();
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b.B();
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$write("*-* All Finished *-*\n");
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$finish;
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endfunction
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endclass
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initial begin
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static A a = A::new();
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a.B();
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end
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endmodule
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