922223a9c3
Removed the VlTriggerVec type, and refactored to use an unpacked array of 64-bit words instead. This means the trigger vector and its operations are now the same as for any other unpacked array. The few special functions required for operating on a trigger vector are now generated in V3SchedTrigger as regular AstCFunc if needed. No functional change intended, performance should be the same. |
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| .. | ||
| _static | ||
| bin | ||
| gen | ||
| guide | ||
| .gitignore | ||
| CONTRIBUTING.rst | ||
| CONTRIBUTORS | ||
| Makefile | ||
| README.rst | ||
| internals.rst | ||
| security.rst | ||
| spelling.txt | ||
| verilated.dox | ||
| xml.rst | ||
README.rst
Verilator Documentation ======================= This folder contains sources for Verilator documentation. For formatted documentation see: - `Verilator README <https://github.com/verilator/verilator>`_ - `Verilator installation and package directory structure <https://verilator.org/install>`_ - `Verilator manual (HTML) <https://verilator.org/verilator_doc.html>`_, or `Verilator manual (PDF) <https://verilator.org/verilator_doc.pdf>`_ - `Subscribe to Verilator announcements <https://github.com/verilator/verilator-announce>`_ - `Verilator forum <https://verilator.org/forum>`_ - `Verilator issues <https://verilator.org/issues>`_