75 lines
1.8 KiB
Systemverilog
75 lines
1.8 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module top #(
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parameter int TOP_PARAM = 42
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) (
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input int top_port_i,
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output int top_port_o
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);
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localparam int TOP_LOCALPARAM = 111;
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int top_tmp;
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mid #(.MID_PARM(TOP_PARAM + TOP_LOCALPARAM)) i_mid_0(top_port_i, top_tmp);
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mid #(.MID_PARM(TOP_PARAM + TOP_LOCALPARAM)) i_mid_1(top_tmp, top_port_o);
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function static void f(input int top_f_port_i, output int top_f_port_o);
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localparam int TOP_F_LOCALPARAM = 1;
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top_f_port_o = top_f_port_i + TOP_F_LOCALPARAM;
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endfunction
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initial begin
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$c("Verilated::scopesDump();");
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module mid #(
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parameter int MID_PARM = 42
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) (
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input int mid_port_i,
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output int mid_port_o
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);
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localparam int MID_LOCALPARAM = 11;
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int mid_tmp_a;
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int mid_tmp_b;
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sub #(.SUB_PARAM(MID_PARM + MID_LOCALPARAM)) i_sub_0(mid_port_i, mid_tmp_a);
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assign mid_tmp_b = mid_tmp_a;
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sub #(.SUB_PARAM(MID_PARM + MID_LOCALPARAM)) i_sub_1(mid_tmp_b, mid_port_o);
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function static void f(input int mid_f_port_i, output int mid_f_port_o);
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localparam int MID_F_LOCALPARAM = 1;
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mid_f_port_o = mid_f_port_i + MID_F_LOCALPARAM;
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endfunction
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endmodule
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module sub #(
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parameter int SUB_PARAM = 42
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) (
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input int sub_port_i,
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output int sub_port_o
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);
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localparam int SUB_LOCALPARAM = 1;
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int sub_tmp;
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assign sub_tmp = sub_port_i + SUB_PARAM;
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assign sub_port_o = sub_tmp + SUB_LOCALPARAM;
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function static void f(input int sub_f_port_i, output int sub_f_port_o);
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localparam int SUB_F_LOCALPARAM = 1;
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sub_f_port_o = sub_f_port_i + SUB_F_LOCALPARAM;
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endfunction
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endmodule
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