67 lines
1.9 KiB
Systemverilog
67 lines
1.9 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Michael Bikovitsky.
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input wire clk
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);
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wire q1;
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pos i_pos(q1, clk);
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wire q2;
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neg i_neg(q2, clk);
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integer cycle = 0;
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always @(posedge clk) begin
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if (cycle == 10) $finish;
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cycle <= cycle + 1;
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end
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always @(q1 or q2) begin
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// q1 should be assigned to 0 on every posedge and to X otherwise.
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// So when the value of q1 changes, *and* clk is positive, we expect
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// q1 to be 1.
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// Same for q2, but on the negedge.
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if (clk && q1) $stop;
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if (!clk && q2) $stop;
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end
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endmodule
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primitive pos (q, clk);
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output q;
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reg q;
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input clk;
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table
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(01) : ? : 0;
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// Explicitly set the output to X on clk 0->X edge.
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// This edge can never happen in Verilator.
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// If all edges *from* 0 are treated as rising edges, this will cause
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// the output to be 1, since we use --x-assign 1, and the test will fail.
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// (Actually this depends on the evaluation order of the always blocks
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// that V3Udp.cpp creates, but at the time of writing they seem to be
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// evaluated in the order of the lines in the table.)
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(0x) : ? : x;
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endtable
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endprimitive
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primitive neg (q, clk);
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output q;
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reg q;
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input clk;
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table
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(10) : ? : 0;
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// Explicitly set the output to X on clk X->0 edge.
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// This edge can never happen in Verilator.
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// If all edges *to* 0 are treated as falling edges, this will cause
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// the output to be 1, since we use --x-assign 1, and the test will fail.
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// (Actually this depends on the evaluation order of the always blocks
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// that V3Udp.cpp creates, but at the time of writing they seem to be
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// evaluated in the order of the lines in the table.)
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(x0) : ? : x;
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endtable
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endprimitive
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