38 lines
670 B
Systemverilog
38 lines
670 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`timescale 1ns / 1ps
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module vip_snitch_cluster #(
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parameter realtime ClkPeriod = 10ns
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) (
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output logic clk_o
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);
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initial begin
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forever begin
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clk_o = 1;
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#(ClkPeriod / 2);
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clk_o = 0;
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#(ClkPeriod / 2);
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end
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end
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initial begin
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#(ClkPeriod * 100);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module t;
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logic clk;
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vip_snitch_cluster #(.ClkPeriod(1ns)) vip (.clk_o(clk));
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endmodule
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