18 lines
425 B
Systemverilog
18 lines
425 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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for (genvar i = 0; i < 4; ++i) begin
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initial $display("Should unroll: %0d", i);
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end
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for (genvar i = 0; i < 5; ++i) begin
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initial $display("Should NOT unroll: %0d", i);
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end
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endmodule
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