26 lines
568 B
Systemverilog
26 lines
568 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// verilator lint_off MULTITOP
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module m1;
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initial begin
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m2.fin;
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end
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endmodule
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module m2;
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task fin;
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$write("*-* All Finished *-*\n");
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$finish;
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endtask
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endmodule
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// Test --top picks this config
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config cfg12;
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design work.m1 m2; // Test both modules listed, library.cell, and cell w/o library
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endconfig
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// verilator lint_on MULTITOP
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