20 lines
446 B
Systemverilog
20 lines
446 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// verilator lint_off MULTITOP
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module m1;
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initial $display("In '%m'");
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endmodule
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module m2;
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initial $display("In '%m'");
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endmodule
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config cfg1;
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design m1 m2;
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endconfig : cfg1 // Test end label
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// verilator lint_on MULTITOP
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