64 lines
1.1 KiB
Systemverilog
64 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// Test several ways of using config to specify different hierarchies When done,
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// have a .py file using --work to select each config, and have a .out golden
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// match file to make sure get expected results.
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module m1;
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initial $stop;
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endmodule
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module c2_bb;
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initial $display("c2_bb %%m=%m %%l=%l");
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endmodule
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module c2_b;
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bb u_bb();
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initial $display("c2_b %%m=%m %%l=%l");
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endmodule
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module t;
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m1 u_1();
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final $write("*-* All Finished *-*\n");
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endmodule
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config cfg21;
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design t;
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instance t.u_1 use work.cfg2 :config;
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endconfig
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config cfg22;
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design t;
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instance t.u_1 use cfg2 :config;
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endconfig
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config cfg31;
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design t;
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cell work.m1 use work.cfg2 :config;
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endconfig
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config cfg32;
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design t;
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cell m1 use cfg2 :config;
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endconfig
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config cfg41;
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design t;
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cell work.m1 use work.cfg2; // :config; implied as no conflict
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endconfig
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// Base usage
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config cfg2;
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design c2_b;
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instance u_bb use work.c2_bb;
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endconfig
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