verilator/test_regress
Geza Lore 5834f22944
Optimize logic and variable removal early in Dfg (#7081)
After conversion of Ast to Dfg, but before synthesizing AstAlways into
primitives, run a pass to remove variables that are not observable, and
all logic that only computes such variables. This can get rid of a lot
of content early so we don't build redundant Dfgs, and also enables
synthesizing always blocks that use temporaries only in some branches,
which will come in a follow up.
2026-02-17 08:28:06 +00:00
..
t Optimize logic and variable removal early in Dfg (#7081) 2026-02-17 08:28:06 +00:00
.gdbinit
.gitignore
CMakeLists.txt Add SPDX copyright identifiers, and get 'reuse' clean. No functional change. 2026-01-26 20:24:34 -05:00
Makefile Internals: make test-diff macOS compatibility fix - again 2026-01-28 11:05:27 +00:00
Makefile_obj Add SPDX copyright identifiers, and get 'reuse' clean. No functional change. 2026-01-26 20:24:34 -05:00
driver.py Fix scope tree in traces in hierarchical mode (#7042) 2026-02-12 20:54:03 -05:00
input.vc
input.xsim.vc