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80 lines
2.3 KiB
Systemverilog
80 lines
2.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// `outer_pkg::Alias::member`, where `Alias` is a typedef in `outer_pkg` that
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// aliases a parameterized class from another package.
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//
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// Until the class is specialized in V3Param the alias's RHS is still a
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// RefDType carrying its own scope, so classOrPackageSkipp() walks to null.
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// Code that tested only Skipp therefore treated the (already resolved) ref as
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// unresolved and re-looked-up its bare name in the referencing module's scope,
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// where `Alias` is not visible - reporting "Package/class for ':: reference'
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// not found". Resolving from a submodule is what exposes it; with the
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// referencing module as top the enclosing scope happens to still find it.
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
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// verilog_format: on
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package base_pkg;
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typedef struct packed {
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int depth;
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int meta;
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} config_t;
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virtual class cfg #(
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parameter config_t c
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);
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localparam int width = $clog2(c.depth);
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typedef logic [width-1:0] data_t;
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typedef struct packed {
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logic [c.meta-1:0] m;
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data_t d;
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} meta_t;
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endclass
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endpackage
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package top_pkg;
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localparam base_pkg::config_t cfgv = '{depth: 512, meta: 4};
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// Typedef alias of a parameterized class, in a different package
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typedef base_pkg::cfg#(cfgv) AliasCFG;
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endpackage
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// Alias-scoped type as a port, and in the body, of an instantiated submodule
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module Leaf (
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input top_pkg::AliasCFG::meta_t in_meta,
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output top_pkg::AliasCFG::data_t out_data
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);
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top_pkg::AliasCFG::meta_t body_meta;
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always_comb begin
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body_meta = in_meta;
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out_data = body_meta.d;
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end
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initial begin
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`checkh($bits(in_meta), 13);
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`checkh($bits(out_data), 9);
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end
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endmodule
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module Mid ();
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top_pkg::AliasCFG::meta_t m;
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top_pkg::AliasCFG::data_t d;
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Leaf leaf (
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.in_meta(m),
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.out_data(d)
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);
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initial m = '0;
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endmodule
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module t;
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Mid mid ();
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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