40 lines
875 B
Systemverilog
40 lines
875 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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interface irq_if (
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input logic clk,
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input logic resetn
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);
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logic irq;
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logic te;
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logic halted;
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logic fault;
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logic wfi;
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clocking cb @(posedge clk);
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default input #1step output #2ns;
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output irq;
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output te;
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input halted;
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input fault;
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input wfi;
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endclocking
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modport DUT_IRQ_PORT(input clk, resetn, output halted, fault, wfi);
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endinterface
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class base_test_class;
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function int foo();
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endfunction
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virtual irq_if.DUT_IRQ_PORT irq_vif;
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function new(string name);
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endfunction
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virtual function void build_phase();
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if (irq_vif == null) begin
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if (foo()) $display();
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end
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endfunction
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endclass
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module tb_top;
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endmodule
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