70 lines
1.8 KiB
Systemverilog
70 lines
1.8 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// Test static get_coverage() with multiple instances
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module t;
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covergroup cg;
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coverpoint data {
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bins low = {[0:1]};
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bins mid = {[2:3]};
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bins high = {[4:5]};
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}
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endgroup
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int data;
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initial begin
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cg cg1, cg2, cg3;
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real type_cov;
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cg1 = new;
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cg2 = new;
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cg3 = new;
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// Initially, no bins covered - should be 0%
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type_cov = cg::get_coverage();
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$display("Initial type coverage: %f", type_cov);
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if (type_cov != 0.0) $stop;
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// Sample cg1 with low bin
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data = 0;
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cg1.sample();
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type_cov = cg::get_coverage();
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$display("After cg1.sample(low): %f", type_cov);
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// 1 bin covered out of 3 = 33.33%
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if (type_cov < 33.0 || type_cov > 34.0) $stop;
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// Sample cg2 with mid bin
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data = 2;
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cg2.sample();
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type_cov = cg::get_coverage();
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$display("After cg2.sample(mid): %f", type_cov);
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// 2 bins covered out of 3 = 66.67%
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if (type_cov < 66.0 || type_cov > 67.0) $stop;
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// Sample cg3 with high bin
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data = 4;
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cg3.sample();
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type_cov = cg::get_coverage();
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$display("After cg3.sample(high): %f", type_cov);
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// 3 bins covered out of 3 = 100%
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if (type_cov < 99.9 || type_cov > 100.1) $stop;
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// Sample cg1 again with same bin - should not change coverage
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data = 1;
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cg1.sample();
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type_cov = cg::get_coverage();
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$display("After cg1.sample(low again): %f", type_cov);
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if (type_cov < 99.9 || type_cov > 100.1) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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