1137 lines
18 KiB
Plaintext
1137 lines
18 KiB
Plaintext
$date
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Tue Apr 14 15:20:33 2026
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$end
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$version
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Generated by VerilatedFst
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$end
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$timescale
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1ps
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$end
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$scope module top $end
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$var wire 1 ! clk $end
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$var wire 5 " state [4:0] $end
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$var wire 1 # fst_inout $end
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$scope module t $end
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$var wire 1 ! clk $end
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$var wire 5 " state [4:0] $end
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$var wire 1 $ fst_inout $end
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$var int 32 % cyc [31:0] $end
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$var logic 1 & rstn $end
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$var real_parameter 64 ' fst_gparam_real $end
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$var real_parameter 64 ( fst_lparam_real $end
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$var real 64 ' fst_real $end
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$var integer 32 ) fst_integer [31:0] $end
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$var bit 1 * fst_bit $end
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$var logic 1 + fst_logic $end
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$var int 32 , fst_int [31:0] $end
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$var shortint 16 - fst_shortint [15:0] $end
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$var longint 64 . fst_longint [63:0] $end
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$var byte 8 / fst_byte [7:0] $end
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$var time 64 0 fst_time [63:0] $end
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$var parameter 32 1 fst_parameter [31:0] $end
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$var parameter 32 2 fst_lparam [31:0] $end
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$var supply0 1 $ fst_supply0 $end
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$var supply1 1 3 fst_supply1 $end
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$var tri0 1 $ fst_tri0 $end
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$var tri1 1 3 fst_tri1 $end
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$var tri 1 4 fst_tri $end
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$var triand 1 5 fst_triand $end
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$var trior 1 6 fst_trior $end
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$var triand 1 7 fst_wand $end
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$var trior 1 8 fst_wor $end
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$var wire 1 9 fst_wire $end
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$var wire 1 : fst_uwire $end
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$scope module test $end
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$var wire 1 ! clk $end
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$var wire 1 & rstn $end
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$var wire 5 " state [4:0] $end
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$var logic 5 ; state_w [4:0] $end
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$attrbegin array unpacked bounds 2 $end
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$scope sv_array state_array $end
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$var logic 5 < state_array[0] [4:0] $end
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$var logic 5 = state_array[1] [4:0] $end
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$var logic 5 > state_array[2] [4:0] $end
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$upscope $end
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$upscope $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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#0
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$dumpvars
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b00000 >
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b00000 =
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b00000 <
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b00000 ;
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0:
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09
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08
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07
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06
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05
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04
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13
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b00000000000000000000000111001000 2
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b00000000000000000000000001111011 1
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b0000000000000000000000000000000000000000000000000000000000000000 0
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b00000000 /
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b0000000000000000000000000000000000000000000000000000000000000000 .
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b0000000000000000 -
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b00000000000000000000000000000000 ,
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0!
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$end
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b10110 =
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1!
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b10001 =
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1!
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