70 lines
1.7 KiB
Systemverilog
70 lines
1.7 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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typedef byte unsigned uint8_t;
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class D;
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rand uint8_t x;
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endclass
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class test;
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D d;
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task run_phase;
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process p;
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uint8_t result;
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string randstate;
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// Pass 1: seed process, create object, randomize, record result
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p = process::self();
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p.srandom(100);
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d = new;
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// Save randstate AFTER d=new (d=new advances process RNG per IEEE 18.14.1)
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randstate = p.get_randstate();
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`checkd(d.randomize(), 1);
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result = d.x;
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// Pass 2: same seed -> same sequence -> same result
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p.srandom(100);
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d = new;
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`checks(p.get_randstate(), randstate);
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`checkd(d.randomize(), 1);
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`checkd(d.x, result);
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// Pass 3: same seed, with intervening task call -> same result
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p.srandom(100);
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other_task();
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d = new;
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`checks(p.get_randstate(), randstate);
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`checkd(d.randomize(), 1);
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`checkd(d.x, result);
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endtask
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task other_task;
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// verilator no_inline_task
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$display("Other task");
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endtask
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endclass
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module t;
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initial begin
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test c;
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c = new;
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c.run_phase();
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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