33 lines
740 B
Systemverilog
33 lines
740 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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task dyn_task(input logic [30:0] data[]);
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$display("%p", data);
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endtask
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task unpacked_task(input logic [30:0] data[3:0]);
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$display("%p", data);
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endtask
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task queue_task(input logic [30:0] data[$]);
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$display("%p", data);
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endtask
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task assoc_task(input logic [30:0] data[int]);
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$display("%p", data);
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endtask
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module t;
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initial begin
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dyn_task(.data($urandom));
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unpacked_task(.data($urandom));
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queue_task(.data($urandom));
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assoc_task(.data($urandom));
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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