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Geza Lore
8546d5db06
The loops modelling the SystemVerilog scheduling regions are no longer generated. They now live in 'VerilatedEvalLoop' in the runtime library. The generated model holds one as a member, passing itself to it, and exposes each evaluation entry point to it as a pure virtual method on VerilatedModel. The model's 'eval' and 'eval_step' remain the top level entry points, and are backward compatible. V3Sched no longer emits '_eval' or '_eval_settle', etc.. Instead every evaluation entry point called from the runtime is enumerated by 'VEval', Scheduling creates all entry points, for all scheduling regions, even if they are empty, and the runtime eval loop calls everything unconditionally. If regions are empty, this is simply a call to an empty function. This will hurt performance on very small models, but should not be noticeable on anything meaningful, so it is likely best to keep to reduce complexity. A scheduling entry points evaluate a single iteration and returns whether it did any work, they are effectively the previous `_eval_phase_*` functions.
.. SPDX-FileCopyrightText: 2003-2026 Wilson Snyder SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 Verilator Documentation ======================= This folder contains sources for Verilator documentation. For formatted documentation see: - `Verilator README <https://github.com/verilator/verilator>`_ - `Verilator installation and package directory structure <https://verilator.org/install>`_ - `Verilator manual (HTML) <https://verilator.org/verilator_doc.html>`_, or `Verilator manual (PDF) <https://verilator.org/verilator_doc.pdf>`_ - `Subscribe to Verilator announcements <https://github.com/verilator/verilator-announce>`_ - `Verilator forum <https://verilator.org/forum>`_ - `Verilator issues <https://verilator.org/issues>`_