mirror of
https://github.com/verilator/verilator.git
synced 2026-09-04 00:30:34 +02:00
Geza Lore
8546d5db06
The loops modelling the SystemVerilog scheduling regions are no longer generated. They now live in 'VerilatedEvalLoop' in the runtime library. The generated model holds one as a member, passing itself to it, and exposes each evaluation entry point to it as a pure virtual method on VerilatedModel. The model's 'eval' and 'eval_step' remain the top level entry points, and are backward compatible. V3Sched no longer emits '_eval' or '_eval_settle', etc.. Instead every evaluation entry point called from the runtime is enumerated by 'VEval', Scheduling creates all entry points, for all scheduling regions, even if they are empty, and the runtime eval loop calls everything unconditionally. If regions are empty, this is simply a call to an empty function. This will hurt performance on very small models, but should not be noticeable on anything meaningful, so it is likely best to keep to reduce complexity. A scheduling entry points evaluate a single iteration and returns whether it did any work, they are effectively the previous `_eval_phase_*` functions.
199 lines
7.7 KiB
Python
Executable File
199 lines
7.7 KiB
Python
Executable File
#!/usr/bin/env python3
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# pylint: disable=C0103,C0114,C0116,C0209,R0914,R0912,R0915,eval-used
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######################################################################
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import argparse
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import collections
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import re
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# from pprint import pprint
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######################################################################
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def profcfunc(filename: str) -> None:
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funcs = {}
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with open(filename, "r", encoding="utf8") as fh:
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for line in fh:
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# %time cumesec selfsec calls {stuff} name
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match = re.match(
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r'^\s*([0-9.]+)\s+[0-9.]+\s+([0-9.]+)\s+([0-9.]+)\s+[^a-zA-Z_]*([a-zA-Z_].*)$',
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line)
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if match:
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pct = float(match.group(1))
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sec = float(match.group(2))
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calls = float(match.group(3))
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func = match.group(4)
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if func not in funcs:
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funcs[func] = {'pct': 0.0, 'sec': 0.0, 'calls': 0}
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funcs[func]['pct'] += pct
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funcs[func]['sec'] += sec
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funcs[func]['calls'] += calls
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continue
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# Older gprofs have no call column for single-call functions
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# %time cumesec selfsec {stuff} name
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match = re.match(r'^\s*([0-9.]+)\s+[0-9.]+\s+([0-9.]+)\s+[^a-zA-Z_]*([a-zA-Z_].*)$',
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line)
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if match:
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pct = float(match.group(1))
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sec = float(match.group(2))
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calls = 1
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func = match.group(3)
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if func not in funcs:
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funcs[func] = {'pct': 0, 'sec': 0, 'calls': 0}
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funcs[func]['pct'] += pct
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funcs[func]['sec'] += sec
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funcs[func]['calls'] += calls
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continue
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# Find modules
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verilated_mods = {}
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for func in funcs:
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# Match only the model entry points: 'eval', 'eval_step', 'eval_end_step',
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# and the 'evalXxx' region entry points, but not e.g. a user's '::evaluate'
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match = re.match(r'([A-Za-z_][A-Za-z_0-9]*)::eval(_step|_end_step|[A-Z][A-Za-z_0-9]*)?\(',
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func)
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if match:
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prefix = match.group(1)
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if prefix.startswith('Verilated'): # Run-time library, not a model
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continue
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if Args.debug:
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print("-got _eval %s prefix=%s" % (func, prefix))
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verilated_mods[prefix] = re.compile(r'^' + re.escape(prefix))
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# pprint(verilated_mods)
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# Sort by Verilog name
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vfuncs = {}
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groups = {}
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groups['type'] = collections.defaultdict(lambda: 0)
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groups['design'] = collections.defaultdict(lambda: 0)
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groups['module'] = collections.defaultdict(lambda: 0)
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for func, func_item in funcs.items():
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pct = func_item['pct']
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vfunc = func
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funcarg = re.sub(r'^.*\(', '', func)
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design = None
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for vde, vde_item in verilated_mods.items():
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if vde_item.match(func) or vde_item.match(funcarg):
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design = vde
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break
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vdesign = "-"
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prof_match = re.search(r'__PROF__([a-zA-Z_0-9]+)__l?([0-9]+)\(', vfunc)
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if design and prof_match:
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linefunc = prof_match.group(1)
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lineno = int(prof_match.group(2))
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vfunc = "VBlock %s:%d" % (linefunc, lineno)
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vdesign = design
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groups['type']["Verilog Blocks under " + design] += pct
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groups['design'][design] += pct
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groups['module'][linefunc] += pct
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elif design:
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vfunc = "VCommon " + func
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vdesign = design
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groups['type']["Common code under " + design] += pct
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groups['design'][design] += pct
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groups['module'][design + " common code"] += pct
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elif re.match(r'(VL_[A-Z0-9_]+|_?vl_[a-zA-Z0-9_]+|Verilated)', vfunc):
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vfunc = "VLib " + func
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groups['type']['VLib'] += pct
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groups['design']['VLib'] += pct
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groups['module']['VLib'] += pct
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elif re.match(r'^_mcount_private', vfunc):
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vfunc = "Prof " + func
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groups['type']['Prof'] += pct
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groups['design']['Prof'] += pct
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groups['module']['Prof'] += pct
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else:
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vfunc = "C++ " + func
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groups['type']['C++'] += pct
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groups['design']['C++'] += pct
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groups['module']['C++'] += pct
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if vfunc not in vfuncs:
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vfuncs[vfunc] = func_item
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vfuncs[vfunc]['design'] = vdesign
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else:
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vfuncs[vfunc]['pct'] += func_item['pct']
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vfuncs[vfunc]['calls'] += func_item['calls']
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vfuncs[vfunc]['sec'] += func_item['sec']
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for ftype in ['type', 'design', 'module']:
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missing = 100
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for item in groups[ftype].keys():
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missing -= groups[ftype][item]
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groups[ftype]["\377Unaccounted for/rounding error"] = missing
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print("Overall summary by %s:" % ftype)
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print(" %-6s %s" % ("% time", ftype))
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for what in sorted(groups[ftype].keys()):
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# \377 used to establish sort order
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pwhat = re.sub(r'^\377', '', what)
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print(" %6.2f %s" % (groups[ftype][what], pwhat))
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print()
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design_width = 1
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for func, func_item in vfuncs.items():
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design_width = max(design_width, len(func_item['design']))
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print("Verilog code profile:")
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print(" These are split into three categories:")
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print(" C++: Time in non-Verilated C++ code")
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print(" Prof: Time in profile overhead")
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print(" VBlock: Time attributable to a block in a" + " Verilog file and line")
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print(" VCommon: Time in a Verilated module," + " due to all parts of the design")
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print(" VLib: Time in Verilated common libraries," + " called by the Verilated code")
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print()
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print(" % cumulative self ")
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print((" time seconds seconds calls %-" + str(design_width) +
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"s type filename and line number") % "design")
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cume = 0.0
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for func in sorted(vfuncs.keys(), key=lambda f: vfuncs[f]['sec'], reverse=True):
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cume += vfuncs[func]['sec']
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print(("%6.2f %9.2f %8.2f %10d %-" + str(design_width) + "s %s") %
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(vfuncs[func]['pct'], cume, vfuncs[func]['sec'], vfuncs[func]['calls'],
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vfuncs[func]['design'], func))
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######################################################################
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######################################################################
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parser = argparse.ArgumentParser(
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allow_abbrev=False,
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formatter_class=argparse.RawDescriptionHelpFormatter,
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description="""Read gprof report created with Verilator --prof-cfuncs
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Verilator_profcfunc reads a profile report created by gprof. The names of
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the functions are then transformed, assuming the user used Verilator's
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--prof-cfuncs, and a report printed showing the percentage of time, etc,
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in each Verilog block.
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For documentation see
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https://verilator.org/guide/latest/exe_verilator_profcfunc.html""",
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epilog="""This program is free software; you can redistribute it and/or modify it
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under the terms of either the GNU Lesser General Public License Version 3
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or the Perl Artistic License Version 2.0.
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SPDX-FileCopyrightText: 2002-2026 Wilson Snyder
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SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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""")
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parser.add_argument('--debug', action='store_const', const=9, help='enable debug')
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parser.add_argument('filename', help='input gprof output to process')
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Args = parser.parse_args()
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profcfunc(Args.filename)
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######################################################################
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# Local Variables:
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# compile-command: "./verilator_profcfunc ../test_regress/t/t_profcfunc.gprof"
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# End:
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