39 lines
899 B
Systemverilog
39 lines
899 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2024 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// Test that array reduction constraints are ignored when array size exceeds --constraint-array-limit
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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class Packet;
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rand int data[32];
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constraint c {
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data.sum() with (item) < 1000;
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}
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function void verify();
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int i;
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i = randomize();
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`checkd(i, 1);
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endfunction
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endclass
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module t;
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initial begin
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Packet p;
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int success_count;
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p = new;
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// Try randomization -- should fail with a warning
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p.verify();
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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