79 lines
1.5 KiB
Systemverilog
79 lines
1.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2021 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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class Cls;
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bit b;
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int i;
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bit [15:0] carray4[4];
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bit [64:0] cwide[2];
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string name;
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real r;
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task debug();
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$display("DEBUG: %s (@%0t) %s", this.name, $realtime, "message");
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endtask
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endclass
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class Base;
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int m_in_base;
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virtual function string fs(input string add = "default");
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static string s_f = "foo";
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fs = {s_f, add};
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endfunction
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virtual function string other(input string add = "default");
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string other = "other";
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other = {other, fs(add)};
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endfunction
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endclass
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class ClsA extends Base;
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int m_in_a;
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Base m_b;
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endclass
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class ClsB extends Base;
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int m_in_b;
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Base m_a;
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endclass
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module t;
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initial begin
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Cls c;
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ClsA ca;
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ClsB cb;
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c = new;
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c.b = '1;
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c.i = 42;
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c.r = 2.2;
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c.name = "object_name";
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c.carray4[0] = 16'h11;
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c.carray4[1] = 16'h22;
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c.carray4[2] = 16'h33;
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c.carray4[3] = 16'h44;
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$display("'%p'", c);
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c.carray4 = '{16'h911, 16'h922, 16'h933, 16'h944};
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$display("'%p'", c);
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c.debug();
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ca = new;
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if (ca.fs("-s") !== "foo-s") $stop; // So not optimized away
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if (ca.other("-o") !== "otherfoo-o") $stop; // So not optimized away
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cb = new;
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$display("'%p'", ca);
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ca.m_b = cb;
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$display("'%p'", ca);
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cb.m_a = ca; // Circular
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$display("'%p'", ca);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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