66 lines
1.1 KiB
Systemverilog
66 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2024 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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module_with_assert module_with_assert (clk);
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module_with_assertctl module_with_assertctl (clk);
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always @(posedge clk) begin
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assert (0);
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end
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always @(negedge clk) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module module_with_assert (
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input clk
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);
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always @(posedge clk) assert (0);
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endmodule
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module module_with_assertctl (
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input clk
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);
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function void assert_off;
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begin
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$assertoff;
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end
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endfunction
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function void assert_on;
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begin
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$asserton;
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end
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endfunction
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function void f_assert;
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begin
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assert (0);
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end
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endfunction
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initial begin
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assert_on();
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assert (0);
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assert_off();
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assert_off();
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assert (0);
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assert_on();
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assert_on();
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assert (0);
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f_assert();
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f_assert();
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assert_off();
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f_assert();
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f_assert();
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end
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endmodule
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