39 lines
770 B
Systemverilog
39 lines
770 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2024 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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module t;
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bit clock = 1'b0;
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bit reset = 1'b0;
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initial begin
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$assertkill;
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#10 reset = 1'b1;
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$display("%t: deassert reset %d", $time, reset);
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#40 $asserton;
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reset = 1'b0;
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$display("%t: deassert reset %d", $time, reset);
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#200 $display("%t: finish", $time);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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always #10 clock = ~clock;
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reg r = 1'b0;
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always @(posedge clock) if (reset) r <= 1'b1;
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assert_test :
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assert property (@(posedge clock) (reset | r))
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else $error("%t: assertion triggered", $time);
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endmodule
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