verilator

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Geza Lore 84dec259c8 Fix constant oversized shifts in V3Premit

- Arithmetic right shift used the MSB of the C++ type as the sign bit,
  instead of the MSB at the Verilog width.
- Constant shift amounts with their top bit set were treated as
  negative, so the oversized shift was emitted as undefined behavior.
- Shifts of an impure operand were replaced by zero, discarding the
  side effects of the operand.

2026-09-25 14:12:00 +01:00