68 lines
1.7 KiB
Systemverilog
68 lines
1.7 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// $bits() of interface member signals used as a child module parameter value.
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// $bits reads the type, not the hierarchical value, so it is legal in a
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// parameter (IEEE 1800-2023 6.20.2 forbids hierarchical values only).
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
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// verilog_format: on
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interface axi_if #(
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parameter int ID_W = 8,
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parameter int ADDR_W = 32
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);
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logic [ID_W-1:0] AWID;
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logic [ADDR_W-1:0] AWADDR;
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logic [7:0] AWLEN;
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endinterface
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module chkmod #(
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parameter int PAYLOAD_WIDTH = 1,
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parameter int EXPECT = 1
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);
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initial `checkh(PAYLOAD_WIDTH, EXPECT);
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endmodule
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module bridge #(
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parameter int EXPECT = 1
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) (
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axi_if axi
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);
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// $bits of a concat of interface members
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chkmod #(
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.PAYLOAD_WIDTH($bits({axi.AWID, axi.AWADDR, axi.AWLEN})),
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.EXPECT(EXPECT)
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) u_concat ();
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// $bits of a single interface member
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chkmod #(
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.PAYLOAD_WIDTH($bits(axi.AWADDR)),
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.EXPECT(EXPECT - 12 - 8)
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) u_single ();
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endmodule
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module t;
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axi_if #(
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.ID_W(12),
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.ADDR_W(64)
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) if0 (); // 12 + 64 + 8 = 84
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axi_if #(
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.ID_W(12),
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.ADDR_W(16)
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) if1 (); // 12 + 16 + 8 = 36
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bridge #(.EXPECT(84)) dut0 (.axi(if0));
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bridge #(.EXPECT(36)) dut1 (.axi(if1));
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initial begin
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#1;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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