42 lines
783 B
Systemverilog
42 lines
783 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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// verilator lint_off MULTITOP
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module dut;
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bit [15:0] acp;
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function void reset();
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acp = 0;
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endfunction
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initial reset();
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endmodule
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module t;
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class Cls;
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static task rw();
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dut.acp++;
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endtask
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endclass
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initial begin
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Cls c;
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c = new;
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c.rw();
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`checkd(dut.acp, 1);
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$finish;
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end
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endmodule
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