66 lines
1.3 KiB
Systemverilog
66 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: FSM coverage begin-wrapped/if-else test
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of either the GNU Lesser General Public License Version 3
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// or the Perl Artistic License Version 2.0.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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module t (
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input logic clk
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);
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typedef enum logic [1:0] {
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S0 = 2'd0,
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S1 = 2'd1,
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S2 = 2'd2
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} state_t;
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logic rst;
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logic sel;
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int cyc;
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state_t state /*verilator fsm_reset_arc*/;
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initial begin
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rst = 1'b1;
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sel = 1'b0;
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cyc = 0;
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end
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always @(posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 1) rst <= 1'b0;
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if (cyc == 2) sel <= 1'b1;
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if (cyc == 3) sel <= 1'b0;
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if (cyc == 6) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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always_ff @(posedge clk) begin
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if (rst) begin
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state <= S0;
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end
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else begin
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case (state)
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S0: begin
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if (sel) begin
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state <= S1;
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end
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else begin
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state <= S2;
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end
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end
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S1: begin
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state <= S0;
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end
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default: begin
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state <= S0;
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end
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endcase
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end
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end
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endmodule
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