verilator/test_regress
Jie Xu 7ef84df852 Add optimization of wires from arrayed cells, msg1447.
Signed-off-by: Wilson Snyder <wsnyder@wsnyder.org>
2014-11-05 21:09:35 -05:00
..
t Add optimization of wires from arrayed cells, msg1447. 2014-11-05 21:09:35 -05:00
.gdbinit Debug: Add default .gdbinit file 2012-03-02 20:59:47 -05:00
.gitignore Tests: Cleanup some old -v3 flags to be -vl 2009-11-24 21:08:42 -05:00
Makefile Copyright year update. 2014-01-06 19:28:57 -05:00
Makefile_obj Copyright year update. 2014-01-06 19:28:57 -05:00
driver.pl Fix clang warnings, bug818. 2014-09-11 21:28:53 -04:00
input.vc Convert repository to git from svn. 2008-06-09 21:25:10 -04:00