38 lines
1.1 KiB
Systemverilog
38 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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`define check_range(gotv,minv,maxv) do if ((gotv) < (minv) || (gotv) > (maxv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d-%0d\n", `__FILE__,`__LINE__, (gotv), (minv), (maxv)); `stop; end while(0);
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// verilog_format: on
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class SimpleRandClass;
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rand bit [7:0] value;
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constraint value_con {value > 0 && value < 200;}
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function new();
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endfunction
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endclass
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module t;
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SimpleRandClass obj;
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int rand_result;
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initial begin
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obj = null;
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rand_result = obj.randomize();
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`checkd(rand_result, 0);
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obj = new();
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rand_result = obj.randomize();
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`checkd(rand_result, 1);
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`check_range(obj.value, 1, 199);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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