35 lines
688 B
Systemverilog
35 lines
688 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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class mbus_seq_item;
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rand logic MREAD;
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endclass
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module t;
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initial begin
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mbus_seq_item req_c[10];
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for (int i = 0; i < 10; i++) begin
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req_c[i] = new;
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if (req_c[i].randomize() with {MREAD == 0;} == 0) begin
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$stop;
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end
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if (req_c[i].MREAD != 0) begin
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$stop;
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end
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if (req_c[i].randomize() == 0) begin
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$stop;
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end
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req_c[i].srandom(42);
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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