32 lines
561 B
Systemverilog
32 lines
561 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
|
|
//
|
|
// This file ONLY is placed under the Creative Commons Public Domain
|
|
// SPDX-FileCopyrightText: 2025 Antmicro
|
|
// SPDX-License-Identifier: CC0-1.0
|
|
|
|
interface ifc;
|
|
int v;
|
|
endinterface
|
|
|
|
module GenericModule #(
|
|
type T,
|
|
type Y = int
|
|
) (
|
|
interface a
|
|
);
|
|
initial begin
|
|
#1;
|
|
if (a.v != 7) $stop;
|
|
end
|
|
endmodule
|
|
|
|
module t;
|
|
ifc inf_inst ();
|
|
GenericModule #(string) genericModule (inf_inst);
|
|
initial begin
|
|
inf_inst.v = 7;
|
|
$write("*-* All Finished *-*\n");
|
|
$finish;
|
|
end
|
|
endmodule
|