62 lines
1.5 KiB
Systemverilog
62 lines
1.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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// AstPow (unsigned**unsigned): 2**n -> 1<<n directly
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class UnsignedPow2;
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rand bit [3:0] n;
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rand bit [15:0] result;
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constraint c { n inside {[0:7]}; result == 16'(2**n); }
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function void check();
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if (result !== (16'h1 << n)) begin
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$display("FAIL UnsignedPow2: result=%0d expected 2**%0d=%0d", result, n, 16'h1 << n);
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$stop;
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end
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endfunction
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endclass
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// AstPowUS (unsigned**signed): 2**n -> n>=0 ? 1<<n : 0
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class SignedExpPow2;
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rand int signed n;
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rand bit [15:0] result;
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constraint c { n inside {[-2:7]}; result == 16'(2**n); }
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function void check();
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bit [15:0] expected;
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expected = (n >= 0) ? (16'h1 << n) : 16'h0;
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if (result !== expected) begin
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$display("FAIL SignedExpPow2: n=%0d result=%0d expected=%0d", n, result, expected);
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$stop;
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end
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endfunction
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endclass
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module t;
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UnsignedPow2 u;
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SignedExpPow2 s;
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initial begin
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u = new;
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repeat (20) begin
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if (u.randomize() == 0) begin
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$display("FAIL: UnsignedPow2.randomize() returned 0");
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$stop;
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end
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u.check();
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end
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s = new;
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repeat (30) begin
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if (s.randomize() == 0) begin
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$display("FAIL: SignedExpPow2.randomize() returned 0");
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$stop;
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end
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s.check();
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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