38 lines
748 B
Systemverilog
38 lines
748 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2025 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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interface Bus;
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logic [15:0] data;
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endinterface
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module t;
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Bus intf ();
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virtual Bus vif;
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virtual Bus vif_arr[5];
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function logic get_vif(inout virtual Bus vif);
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vif = intf;
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return 0;
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endfunction
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initial begin
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if (get_vif(vif));
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while (get_vif(vif));
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do; while (get_vif(vif));
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for (int i = 0; get_vif(vif); i++);
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foreach (vif_arr[i]) begin
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if (vif_arr[i]) begin
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$display("vif_arr[%0d]=%p", i, vif_arr[i]);
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end
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else begin
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vif_arr[i] = intf;
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end
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end
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end
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endmodule
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