56 lines
1.3 KiB
Systemverilog
56 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2010 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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package some_pkg;
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localparam FOO = 5;
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localparam BAR = 6;
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typedef enum int {QUX = 7} pkg_enum_t;
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endpackage
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module t (
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input clk
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);
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int cyc = 0;
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logic [31:0] package_array[8];
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always_comb
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package_array = '{
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1: 32'h1111,
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some_pkg::FOO: 32'h9876,
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some_pkg::BAR: 32'h1212,
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some_pkg::QUX: 32'h5432,
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default: 0
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};
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always @(posedge clk) begin
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`checkh(package_array[0], 32'h0);
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`checkh(package_array[1], 32'h1111);
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`checkh(package_array[2], 32'h0);
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`checkh(package_array[3], 32'h0);
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`checkh(package_array[4], 32'h0);
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`checkh(package_array[5], 32'h9876);
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`checkh(package_array[6], 32'h1212);
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`checkh(package_array[7], 32'h5432);
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end
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always @(posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 2) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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