40 lines
714 B
Systemverilog
Executable File
40 lines
714 B
Systemverilog
Executable File
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2017 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t();
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parameter LEN1 = 8;
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test #(
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.LEN(LEN1),
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.LST('{LEN1{0}})
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)
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inst1();
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parameter LEN2 = 3;
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test #(
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.LEN(LEN2*2),
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.LST('{LEN2*2{0}})
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)
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inst2();
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test #(
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.LEN(LEN1 + LEN2),
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.LST('{(LEN1+LEN2){0}})
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)
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inst3();
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test #(
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.LEN(LEN1 + LEN2),
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.LST('{LEN1{0}, LEN2{1}})
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)
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inst4();
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endmodule
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module test #(
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parameter LEN = 4,
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parameter LST[LEN] = '{LEN{0}}
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)();
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endmodule
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