37 lines
1.2 KiB
Python
37 lines
1.2 KiB
Python
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of either the GNU Lesser General Public License Version 3
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# or the Perl Artistic License Version 2.0.
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# SPDX-FileCopyrightText: 2026 Wilson Snyder
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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def run(test):
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(fmt, ) = test.parse_name(r"t_trace_struct_alias_([a-z]+)")
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test.top_filename = "t/t_trace_struct_alias.v"
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test.golden_filename = test.py_filename.rpartition(fmt)[0] + fmt + ".out"
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flags = ["--cc", f"--trace-{fmt}", "--trace-structs"]
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test.compile(verilator_flags2=flags)
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test.execute()
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if fmt == "vcd":
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codes = test.vcd_extract_codes(test.trace_filename)
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test.vcd_check_not_aliased(codes, "top.t.s1.a", "top.t.s2.a")
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test.vcd_check_aliased(codes, "top.t.s3.a", "top.t.alias_of_s3a")
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test.vcd_check_aliased(codes, "top.t.s4.a", "top.t.s5.a")
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test.vcd_check_aliased(codes, "top.t.s4.b", "top.t.s5.b")
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test.vcd_check_aliased(codes, "top.t.s6.a", "top.t.source_val")
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test.trace_identical(test.trace_filename, test.golden_filename)
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test.passes()
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