20 lines
365 B
Systemverilog
20 lines
365 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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interface str_if;
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string s;
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endinterface
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module t;
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str_if sif();
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virtual str_if vif = sif;
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initial begin
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vif.s = "hello";
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$finish;
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end
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endmodule
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