42 lines
776 B
Systemverilog
42 lines
776 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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interface my_if;
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logic clk = 0;
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bit clk_active = 0;
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initial begin
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wait (clk_active);
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forever #5 clk = ~clk;
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end
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function void start_clk();
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clk_active = 1;
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endfunction
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endinterface
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class Driver;
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virtual my_if vif;
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task run();
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#10;
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vif.start_clk();
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endtask
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endclass
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module t;
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my_if intf();
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my_if intf_unused(); // Second instance triggered the bug
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initial begin
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automatic Driver d = new;
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d.vif = intf;
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d.run();
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repeat (4) @(posedge intf.clk);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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