Krzysztof Bieganski 701fa5438a Fix output clockvar overwriting signal (#5320) (#5347) ...

Signed-off-by: Krzysztof Bieganski <[email protected]>

2024-08-08 21:48:25 +01:00

..

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Fix output clockvar overwriting signal (#5320) (#5347)

2024-08-08 21:48:25 +01:00

.gdbinit

Revert .gdbinit modified by accident. (#4330)

2023-06-30 16:57:31 -04:00

.gitignore

Ignore some files generated by modelsim (#2669)

2020-12-05 21:55:56 -05:00

CMakeLists.txt

Copyright year update

2024-01-01 03:19:59 -05:00

driver.pl

Tests: Fail with test.pl-file-needs-have_solver()-call if forget have_solver()

2024-07-13 08:55:06 -04:00

input.vc

Tests: Avoid verilated.v include in most tests

2024-02-27 18:08:37 -05:00

input.xsim.vc

Tests: Avoid verilated.v include in most tests

2024-02-27 18:08:37 -05:00

Makefile

Make installation relocatable, and the installation testable (#4927)

2024-03-01 00:08:28 +00:00

Makefile_obj

Copyright year update

2024-01-01 03:19:59 -05:00