70 lines
1.5 KiB
Systemverilog
70 lines
1.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2010 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk,
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input rst_both_l,
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input rst_sync_l,
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input rst_async_l,
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input d
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);
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reg q1;
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reg q2;
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always @(posedge clk) begin
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if (~rst_sync_l) begin
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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q1 <= 1'h0;
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// End of automatics
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end
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else begin
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q1 <= d;
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end
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end
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always @(posedge clk) begin
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q2 <= (rst_both_l) ? d : 1'b0;
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if (0 && q1 && q2);
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end
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reg q3;
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always @(posedge clk or negedge rst_async_l) begin
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if (~rst_async_l) begin
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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q3 <= 1'h0;
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// End of automatics
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end
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else begin
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q3 <= d;
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end
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end
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reg q4;
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always @(posedge clk or negedge rst_both_l) begin
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q4 <= (~rst_both_l) ? 1'b0 : d;
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end
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// Make there be more async uses than sync uses
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reg q5;
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always @(posedge clk or negedge rst_both_l) begin
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q5 <= (~rst_both_l) ? 1'b0 : d;
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if (0 && q3 && q4 && q5);
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end
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// Issue #7980 - should not cause a warning
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logic mirror;
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logic [15:0] settle;
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// Level-sensitive block (NO posedge/negedge): a plain combinational observer of `value`.
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always @(mirror) $display("%0d", mirror);
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always_ff @(posedge clk) begin
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mirror <= d;
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if (mirror != 1'd0) settle <= settle + 16'd1;
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end
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endmodule
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