77 lines
1.5 KiB
Systemverilog
77 lines
1.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%h' exp='%h'\n", `__FILE__,`__LINE__, (gotv), (expv)); end while(0);
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module t;
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logic clk;
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int i_header;
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int i_len;
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int i_data;
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int i_crc;
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int o_header;
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int o_len;
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int o_data;
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int o_crc;
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pkt_if pkt_if_init (clk);
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//this will not compile without -fno-life
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initial begin
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byte byte_pkt[$];
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//---------------------- STREAM WITH INTERFACE -------------------
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//using this forces verilator to a AstSel Node into a Stream Node
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#0 //make sure we dont optimize it all away in v3life
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pkt_if_init.s.extra = 8'hd;
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byte_pkt = {>>{pkt_if_init.s.extra}};
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if(8'hd == {>>{byte_pkt}}) begin
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$write("*-* All Finished *-*\n");
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$finish();
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end
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end
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endmodule
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interface pkt_if (
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input wire clk
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);
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typedef struct packed {
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logic [31:0] extra;
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logic [31:0] empty;
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logic [31:0] data;
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logic valid;
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logic sop;
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logic eop;
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} avst_s;
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avst_s s;
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logic ready;
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// Read-Only Helper Signals
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logic sop_pulse;
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logic eop_pulse;
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modport src (
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output s,
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input ready,
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input sop_pulse, eop_pulse
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);
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modport snoop (
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input s,
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input ready,
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input sop_pulse, eop_pulse
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);
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modport sink (
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input s,
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output ready,
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input sop_pulse, eop_pulse
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);
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endinterface
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