70 lines
1.4 KiB
Plaintext
70 lines
1.4 KiB
Plaintext
$version Generated by VerilatedVcd $end
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$timescale 1ps $end
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$scope module cpptop $end
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$var wire 1 % clk $end
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$scope module t $end
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$var wire 1 % clk $end
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$var wire 32 " cyc [31:0] $end
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$scope module sub_a $end
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$var wire 32 & ADD [31:0] $end
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$var wire 32 " cyc [31:0] $end
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$var wire 32 # value [31:0] $end
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$upscope $end
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$scope module sub_b $end
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$var wire 32 ' ADD [31:0] $end
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$var wire 32 " cyc [31:0] $end
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$var wire 32 $ value [31:0] $end
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$upscope $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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#0
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b00000000000000000000000000000000 "
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b00000000000000000000000000001010 #
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b00000000000000000000000000010100 $
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0%
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b00000000000000000000000000001010 &
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b00000000000000000000000000010100 '
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#1
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b00000000000000000000000000000001 "
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b00000000000000000000000000001011 #
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b00000000000000000000000000010101 $
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1%
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#2
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0%
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#3
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b00000000000000000000000000000010 "
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b00000000000000000000000000001100 #
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b00000000000000000000000000010110 $
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1%
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#4
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0%
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#5
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b00000000000000000000000000000011 "
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b00000000000000000000000000001101 #
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b00000000000000000000000000010111 $
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1%
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#6
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0%
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#7
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b00000000000000000000000000000100 "
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b00000000000000000000000000001110 #
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b00000000000000000000000000011000 $
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1%
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#8
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0%
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#9
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b00000000000000000000000000000101 "
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b00000000000000000000000000001111 #
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b00000000000000000000000000011001 $
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1%
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#10
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0%
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#11
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b00000000000000000000000000000110 "
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b00000000000000000000000000010000 #
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b00000000000000000000000000011010 $
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1%
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