37 lines
937 B
Systemverilog
37 lines
937 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input wire clk
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);
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integer cyc = 0;
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reg [31:0] acc;
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task automatic add_pair(input [31:0] a, input [31:0] b, inout [31:0] sum);
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// verilator no_inline_task
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sum = sum + a + b;
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endtask
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always @(posedge clk) begin
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cyc <= cyc + 1;
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acc = 0;
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add_pair(cyc[31:0], 32'd1, acc); // + cyc + 1
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add_pair(32'd1000, cyc[31:0], acc); // + 1000 + cyc
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// acc = (cyc + 1) + (1000 + cyc) = 2*cyc + 1001
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if (cyc > 1) begin
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if (acc !== (2 * cyc[31:0] + 32'd1001)) begin
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$write("%%Error: cyc=%0d acc=%0d expected %0d\n", cyc, acc, 2 * cyc + 1001);
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$stop;
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end
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end
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if (cyc == 20) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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