76 lines
2.1 KiB
Systemverilog
76 lines
2.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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// verilog_format: on
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module t;
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logic clk = 1'b0;
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always #5 clk = ~clk;
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logic [31:0] cyc = 0;
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logic [3:0] idx;
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assign idx = cyc[3:0];
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// V3Case lowers this to a 512-bit constant-pool lookup table before V3Dead
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// calls AstConstPool::rebuildVarScopesAndCache().
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logic [31:0] case_word;
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always_comb
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case (idx)
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4'h0: case_word = 32'h00000000;
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4'h1: case_word = 32'h00000001;
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4'h2: case_word = 32'h00000002;
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4'h3: case_word = 32'h00000003;
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4'h4: case_word = 32'h00000004;
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4'h5: case_word = 32'h00000005;
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4'h6: case_word = 32'h00000006;
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4'h7: case_word = 32'h00000007;
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4'h8: case_word = 32'h00000008;
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4'h9: case_word = 32'h00000009;
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4'ha: case_word = 32'h0000000a;
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4'hb: case_word = 32'h0000000b;
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4'hc: case_word = 32'h0000000c;
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4'hd: case_word = 32'h0000000d;
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4'he: case_word = 32'h0000000e;
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default: case_word = 32'h0000000f;
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endcase
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localparam logic [511:0] TABLE = {
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32'h0000000f,
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32'h0000000e,
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32'h0000000d,
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32'h0000000c,
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32'h0000000b,
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32'h0000000a,
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32'h00000009,
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32'h00000008,
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32'h00000007,
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32'h00000006,
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32'h00000005,
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32'h00000004,
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32'h00000003,
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32'h00000002,
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32'h00000001,
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32'h00000000
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};
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// V3Premit extracts this matching wide constant after V3Dead recached the
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// const-pool contents created by V3Case.
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logic [31:0] static_word;
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assign static_word = TABLE[{idx, 5'b0} +: 32];
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always @(posedge clk) begin
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`checkh(case_word, static_word);
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cyc <= cyc + 32'd1;
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if (cyc == 32'd32) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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