51 lines
1.1 KiB
Systemverilog
51 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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module t;
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reg clk = 1;
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reg [7:0] d = 0;
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reg [7:0] q = 0;
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// Clock generation
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always #0.5 clk = ~clk;
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// Input signal generation
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initial begin
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// verilator lint_off INITIALDLY
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d <= 0;
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repeat (5) @(posedge clk);
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d <= 1;
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@(posedge clk);
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d <= 2;
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@(posedge clk);
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d <= 3;
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@(posedge clk);
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d <= 4;
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@(posedge clk);
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d <= 0;
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repeat (5) @(posedge clk);
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$finish;
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end
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// Unit under test (flip-flop)
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always @(posedge clk) q <= d;
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always @(negedge clk) begin
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$display("[%0t] d=%x q=%x", $time, d, q);
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if (d == 1) `checkd(q, 0);
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if (d == 2) `checkd(q, 1);
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if (d == 3) `checkd(q, 2);
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if (d == 4) `checkd(q, 3);
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end
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endmodule
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