45 lines
1.2 KiB
Systemverilog
45 lines
1.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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// verilog_format: on
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module t;
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logic clk = 1'b0;
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always #5 clk = ~clk;
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logic [31:0] cyc = 0;
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// Converted to case table in const pool, but proven unused by Dfg
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logic [15:0] out;
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always_comb begin
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case (cyc[3:0])
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4'd0: out = 16'h1111;
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4'd1: out = 16'h2222;
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4'd2: out = 16'h4444;
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4'd3: out = 16'h8888;
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default: out = 16'h0f0f;
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endcase
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end
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// Complicated way to write constant 0 that only Dfg can decipher
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wire [63:0] convoluted_zero = (({64{cyc[0]}} & ~{64{cyc[0]}}));
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wire logic [15:0] zero = &convoluted_zero ? out : 16'd0;
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// Test driver/checker
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always @(posedge clk) begin
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`checkh(zero, 16'd0);
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cyc <= cyc + 32'd1;
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if (cyc == 32'd32) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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