21 lines
744 B
Systemverilog
21 lines
744 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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module t (input clk);
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logic a;
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// A strong always must be bounded (IEEE 1800-2023 16.12.11): there is no bare
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// s_always grammar production, and s_always [m:$] is the explicit "// Illegal"
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// example (p5). Both forms are rejected.
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assert property (@(posedge clk) s_always a);
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assert property (@(posedge clk) s_always [2:$] a);
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// A weak always range may only place $ on the high bound; an unbounded low
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// bound is not a legal cycle_delay_const_range_expression.
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assert property (@(posedge clk) always [$:5] a);
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endmodule
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