31 lines
571 B
Systemverilog
31 lines
571 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2025 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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interface b_if;
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int x = 1;
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endinterface
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module t;
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bind m b_if if_bind ();
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m #(.p(2)) m_i ();
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typedef virtual b_if vif_t;
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initial begin
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vif_t vif = t.m_i.if_bind;
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int y = t.m_i.if_bind.x;
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if (vif.x != 1) $stop;
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if (y != 1) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module m #(
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parameter p = 1
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) ();
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endmodule
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