verilator/test_regress/t/t_trace_ub_misaligned_addre...

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809 B
Python
Executable File

#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of either the GNU Lesser General Public License Version 3
# or the Perl Artistic License Version 2.0.
# SPDX-FileCopyrightText: 2024 Wilson Snyder
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.top_filename = "t/t_trace_ub_misaligned_address.v"
test.compile(verilator_flags2=["--binary --trace-vcd", "--runtime-debug"])
test.execute(aslr_off=True)
# Make sure that there are no additional messages (such as runtime messages
# regarding undefined behavior).test.files_identical(test.obj_dir + "/vlt_sim.log", test.golden_filename, "logfile")
test.passes()