35 lines
667 B
Systemverilog
35 lines
667 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2025 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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class Foo;
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bit [2:0] x = 0;
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function int get();
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x += 1;
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return int'(x);
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endfunction
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function bit [2:0] get2();
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x += 1;
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return x;
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endfunction
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endclass
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module t;
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Foo foo;
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int x[5] = {1, 2, 3, 4, 5};
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initial begin
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foo = new;
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if (x[foo.get()] != 2) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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always begin
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if (x[foo.get2()] != 3) $stop;
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end
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final begin
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if (x[foo.get()] != 4) $stop;
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end
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endmodule
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