26 lines
520 B
Systemverilog
26 lines
520 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2023 Antmicro Ltd
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer i = 0;
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integer q[$] = {0, 1};
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always @(posedge clk) begin
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$display("%p", q[i:i+1]);
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q.push_back(i+2);
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i++;
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if (i >= 3) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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